A relatively new type of programmable integrated circuit, called a Programmable System Device (PSD), includes an erasable programmable read-only memory (EPROM), a static random access memory (SRAM), a programmable logic device (PLD), and random control logic. The PLD within the PSD is used as an address decoder, selecting different devices outside and within the PSD for access and use. Because of its function, the PLD is also called a Programmable Mapping Decoder (PMD). The PMD provides signals, i.e. chip select output (CSO) signals, on off-chip output lines for selecting devices that are outside the PSD. The PMD also provides signals for internally selecting different blocks that are within the PSD, such as EPROMs, SRAMs and input/output (I/O) ports.
A generic PMD 100, as illustrated in FIG. 1, has an array 101 of programmable storage elements which may be EPROMs, electrically erasable read only memories (EEPROMs), static random access memories (SRAMs), flash EEPROMs, or read only memories (ROMs). Individual storage elements are identified by their respective rows and columns, where the total number of rows is R and the total number of columns is C. During a power-down mode, elements in the PMD, e.g. bit lines, sense amplifiers, nodes, or gates (not shown) are forced to predetermined low power states. In this manner, all elements drawing power will be forced to known states not drawing power.
For example, during a power-down mode, PMD100 is generally forced to a known state in two areas. First, an input signal is forced on line 106. In the illustrative generic configuration shown in FIG. 1, the power-down mode is triggered by a chip enable (CE) signal from pin 109. The power-down and the power-up modes are contingent upon this signal, not upon disconnection or connection to a voltages source, respectively. Note that PMD 100 may also be forced to a known state by forcing internal signals within the array 101 of programmable storage elements (which is not shown to simplify the figure). Second, the signals on lines 102 are forced to a known state. In the power-down mode, these output signals preferably result in a deselect state. Specifically, all devices driven by PMD 100 are "off". Note these output signals may be high or low. Hence, in summary, in the power-down mode, at least two areas of PMD100 are forced to particular values.
The power-up mode is typically accomplished using one of two methods. In one method, the power-up sequence is uncontrolled. In other words, all elements previously forced in the power-down mode are released at the same time. In this method, propagation times of the CE signal through each element in the PMD became critical. For example, referring to the specific elements in FIG. 1, depending on the circuitry (i.e. transistor-transistor-logic (TTL) circuits 104) and the layout (i.e. positioning-of buffer 107 in relation to TTL circuits 104 and input buffers 103), signals from the array 101 of programmable storage elements may reach the AND gates 110 after the signal from buffer 107 is received. Hence, the output signals from AND gates 110 on lines 102 go through transitions from the beginning of the power-up mode until the end of the power-up mode when all signals are stabilized. These signal transitions are called glitches. Note that even two PMDs identically designed may or may not have this problem due to temperature and power supply variations.
In another method to power-up, the power-up sequence is controlled. However, in this method, unnecessary time delays are generally introduced to ensure no glitches occur. For example, the forced signals on lines 102 (in this instance, forced by the signal on line 111) may be released only after signals propagated through input buffers 103 and array 101 are stabilized. In order for no glitches to occur, the delay time must be estimated conservatively. Hence, the introduction of unnecessary time delays.
Accordingly, there is a need for an improved programmable array which eliminates glitches without adding an unnecessary time delay.